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Tessera Technologies Inc. Message Board

  • jacosa jacosa Sep 30, 2011 12:43 PM Flag

    Connection densities

    This was prompted by Diodes Inc's latest announcement of an LED driver. Diodes tends to make leading, not bleeding edge small parts. The external connection pitch is 0.65 mm (probably 0.5 internaly).

    So I looked for specs on some highly sophisticated parts: Qualcomm's last-generation smartphone processor had lots of connections at a 0.4 mm pitch. They are shipping a newer one, but I can't find physical specs on it. It has to have more connections, and I doubt that it's larger. I'll guess 0.25 mm or better.

    The interesting thing is that these are pretty much the absolute limits of ball grid array packaging for sophisticated chips. Electromigration starts to significantly affect the failure rate in use, and mechanical issues with fragile low-k dielectrics and heat-sensitive high-k dielectrics approach the limits of tolerability (denser means lower bumps with less area). Something has to give, and I'm predicting that it won't be the end of connection density increases.

    MicroPILR is ready to go at 0.15 mm pitch, and close at 0.12 mm. Anyone seen devices in that range yet? Any clues on how they do it?

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