What is the tradeoff between a first and second level TLB?
My concern is that the second level TLB causes too many cache unnecessary read hits. Of course, this can usually only be tested with empirical vallidation suites which try to randomly hammer the address space with pseudo-randomized cache line addresses. (As you know, a cache hit or miss is qualified by a subset of the physical address bits in the target address.)
So, how to randomize an address test pattern that roughly mimics that of a typical operating system core. Or, for the purist, totally randomize address space cache hits and misses to equal the addressibility of the qualified bits presented to the cache.
Or, crudely compare the performance of a 2 level TLB CPU core with a single level TLB. This is, of course, costly, since much time would have to be spent modifying the core model to support vastly different MBus management architectures and/or turn silicon with both models and DV each at great cost and with the potential of dead R1 test silicon.
If you know so much about semiconductors then why do you bash Intel so much? It's my understanding Intelis the number one semiconductor maker in the world. They have a very good balance sheet and much cash on hand in the financial crisis. You may know how to cut and paste but you surely can't read a balance sheet.
I didn't bash INTC. I told the truth as I see it. INTC is dead money. They have lower guidance, admittedly more than needed employees, no products in the pipeline, trench warfare with AMD, stuffed channels, GHz wall, process wall, disgruntled employees, retiring CTO, possible immigration problems, $1B investment loss, many canceled initiatives and on and on and on.