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  • wallisweaver wallisweaver Nov 22, 2011 12:04 AM Flag

    More Bad Fabrication News for ARM/TSMC

    [EUV still isn't ready for prime time. This presents a significant problem for TSMC, where they need the technology for 20nm production. If it's not ready there will either be a significant delay in moving to 20nm or costs will be much higher due to the need for double patterning instead of EUV. Intel won't need EUV until it gets to 10nm fabrication.]

    [Instead of ARM's roadmap ending with 20nm fabrication, this could mean that it ends with 28n fabrication.]

    "Extreme-violet (EUV) lithography, the next big step in chip manufacturing, is still not ready for prime time. This would mean that global chip makers who plan to use EUV manufacturing technology may have to leverage more complicated, as well as expensive, strategies to extend the current lithography tools they are using, such as double patterning. Even worse, the EUV gap also threatens the fundamental economics of the semiconductor manufacturing supply chain.

    EUV was originally planned for production use as far back as 2005. It had been expected to be ready for 22nm chip manufacture, which Intel is initiating this year. However, Intel Corp. now plans to extend optical lithography through the 14nm node and switch to EUV as its mainstream production approach at the 10nm node, starting in the second half of 2015. Samsung plans to insert EUV into volume manufacturing as soon as 2013.

    Chip makers need EUV to be ready well in advance of when they plan to use it in volume manufacturing so they can establish chip design rules and tweak their manufacturing processes. There are still challenges for EUV, including the development of better photomask inspection and repair tools and more-sensitive photoresists.

    By far, the biggest hurdle to rolling out EUV in volume production is wafer throughput on EUV tools, a metric that remains far lower than what is needed to make EUV-based manufacturing viable. The gating factor on throughput has been the lack of a EUV light source that can deliver the necessary power and reliability.

    "I think it's pretty clear that the EUV source is not going to be ready at the required power and reliability in the next couple of years," said Franklin Kalk, chief technology officer at Toppan Photomask. "With the first production tool delivery now scheduled for late 2012, and production integration following that, people who want to ramp EUV in 2013 are not going to be able to.""

    http://www.eetasia.com/ART_8800656186_480200_NT_a81058ff.HTM

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    • "“We expect A-15 to be sampling in the first half of next year, to be in full production in Q4 2012, and to be out in hand-sets by the end of next year,” says Howarth.'"

      ***

      This is hilarious. They don't even expect full production of 28nm in 2012 and now they tell us they are going to have full 20nm production. Are they just going to skip 28nm?

      I'll believe it when they start selling it...

    • http://www.electronicsweekly.com/Articles/21/11/2011/52328/arm-and-tsmc-moving-fast-to-20nm.htm

      'ARM and TSMC are moving fast to get Cortex A-15 out on a 20nm process. A chip has already been taped out and an ARM process team has been set up in Taiwan to handle the transition.

      “The 20nm tape-out is a test vehicle,” ARM’s executive vp for marketing, Lance Howarth, tells EW, “the expectation is that we’re a year away from 20nm as a production technology.”

      The rationale for the tape-out is that: “We need to have proven IP and to prove the design flows, to verify the RTL and make sure it all works well on 20nm,” says Howarth, “because the interdependencies between process technology and the IP are increasing all the time.”

      “We’ve tied that in with opening a small design centre in Taiwan’s Hsinchu Science Park,” adds Howarth, “we’re putting in expertise in terms of physical IP from our PIPD division, process guys and graphics guys looking at the deployment of our IP on advanced processes. Initially we’ll have eight guys rising to 12.”

      In an age when some process transitions don’t deliver much in terms of increased performance due to higher leakage, TSMC’s 20nm process is expected to deliver some surprisingly significant gains.

      Maria Marced, President of TSMC Europe says: “Compared to 28nm the 20nm process is expected to deliver a 25% improvement in power consumption, a 15-20% improvement in performance and a 1.9x increase in density. The plan is to introduce the first version of 20nm in the second half of 2012.”

      Howarth is impressed by TSMC’s moves on 20nm. “TSMC are quite aggressive in pushing 20nm, they are accelerating 20nm development,” he says, “people think TSMC are responding well in respect to 20nm and don’t think Intel are as advanced in 20nm compared to TSMC. Their vision is that finfet comes in at 20nm (at Intel) but the advantage of finfet will be marginal.”

      Asked if ARM might consider fully depleted SOI (FDSOI) as an alternative to finfet, Howarth responds: “We have a team in Grenoble specifically looking at SOI and have been for some time. The jury is still out on the mass adoption of SOI.”

      Earlier this week, at the European Nanoelectronics Forum in Dublin, a report on the EU’s Catrene SOI development project involving AMD, GloFo, ST, Soitec, Siltronic and others stated that, at 20nm, finfet and fully depleted SOI are on a par.

      Delivering the report, ST’s Gilles Thomas said: "Don’t panic, the transistor architecture on finfet and FDSOI are the same but for a rotation of 90º. "

      For the time being, ARM’s focus is on getting out Cortex A-15 on 28/32nm processes.

      “We expect A-15 to be sampling in the first half of next year, to be in full production in Q4 2012, and to be out in hand-sets by the end of next year,” says Howarth.'

    • Wallis... you COWARD !!!!

      Repeat 6th time this thread:

      What lithography will INtel use for 22nm & 14nm...

    • Yep, fanboi, you got me good.

      Here I was trying to keep ARM's fabrication problems under wraps and you just blew me right out of the water.

      Pretty sure everyone knows now.

      They know about the problems with 28nm and how it will be the end of 2012 before revenues reach 10 percent.

      They know about the extra costs with double patterning and the delays on EUV at 20nm and that no one knows when volume production will take place.

      They know that ARM/TSMC has no technology with which to move to 14nm nor the money to keep building fabs at a competitive rate.

      Yep, the cat's out of the bag now. Silly me thinking I could conceal it.

      You really got me on this one.

      You're a genius, Gumpboi...

    • Wallis, GOTCHA GOOD !!!!

      repeat 5th time this thread:

      What lithography will INtel use for 22nm & 14nm...

    • Intel is using the lithography on 14nm that TSMC can't figure out how to use on 14nm or maybe 20nm for that matter. We'll have to see.

      I can't help but notice how you seem to be sensitive to ARM's serious fabrication problems. Are you trying to keep it quiet?

      Then maybe you shouldn't be talking about it constantly on the Intel message board.

      Just a thought...

    • Wallis,

      repeat the question 4th time:

      What lithography is INtel using for 22nm & 14nm ??

    • "What lithography is INtel using for 22nm & 14nm..."

      ***

      If it's just the same then why can't TSMC do it at 14nm, nitwit???

      They've already admitted they can't. Get used to it...

    • "To enable 22-nm, Intel must do a ''couple more’’ double patterning steps, Bohr said. But in all, the company will use standard fab tools in the technology and the process cost adder is only 2 to 3 percent."

    • Intel's manufacturing is simply better. That's why they can use the existing lithography all the way through 14nm and TSMC has admitted that they can't.

      ***

      "The main reason they want to use EUV is actually pretty simple: Higher throughput, especially when you go to 16-nm and beyond.

      To do 20nm with DUV, you have to do double patterning, which means you're literally doing each layer twice (or at least the critical layers), thus cutting your throughput in half. If you go to 16nm, you will have to do triple-patterning, so your throughput is a 1/3rd. Adding to this problem, is the fact that as you increase the number of patterning steps for a single layer, you're also drastically decreasing your process margin, so your yield will take a hit.

      If you do EUV on the other hand, you can simple do a single exposure per layer, which is faster. Or at least it will be, once the technology reaches maturity."

      http://forums.anandtech.com/archive/index.php/t-2147013.html

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