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Intel Corporation Message Board

  • getanid61 getanid61 Dec 23, 2012 10:43 AM Flag

    ARM and Cadence Tape Out First 14nm FinFET Test Chip

    *AMD and Cadence taped out the first ARM Cortex-A7 test chip in
    Samsung's 14-nanometer FinFET process.*

    According to ARM, the chip included the Cortex-A7 processor itself,
    as well as Artisan standard-cell libraries, "next-generation" memories,
    and general purpose IOs.

    "This is an important milestone in our efforts to enable our silicon
    partners for continued low-power leadership in future generations of
    innovative, energy-efficient mobile products, said Dipesh Patel, vice
    president and general manager of the Physical IP Division at ARM.
    "Taping out ARMs most energy-efficient applications processor on
    Samsung's advanced low-power manufacturing process was achieved
    through the combination of leading-edge technology and R&D excellence,
    as well as a deep and early collaboration with Samsung and Cadence."

    ARM said that the process is targeting high-density, high-performance
    and ultra-low power SoCs for "future smartphones, tablets and all other
    advanced mobile devices". There was no information when 14 nm ARM
    processors will become available.

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    • From the EETIMES
      IBM, Intel face off at 22 nm

      Rick Merritt

      12/10/2012 8:29 PM EST


      SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22-nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here Monday (Dec. 10). Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.

      IBM said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm node. Intel retains an edge with several 22-nm chips already in volume production, and disclosure at IEDM of a variant of the process for SoCs for a wide range of applications.

      The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” Mark Bohr, head of Intel’s process technology development group, said in a brief interview. The process is geared for a much wider array of designs than that of IBM, he added.

      Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.

      Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

      “Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

    • From EETIMES

      Intel's 22-nm tri-gate SoC, how low can you leak?

      Sylvie Barak

      12/10/2012 4:30 PM EST

      Scalable roadmap

      Ultimately, said Bohr, the distinction between regular processors and SoCs is blurring, with even CPUs like Ivy Bridge incorporating typical SoC elements like multiple computing cores, graphics, high performance IO circuits and cache. SoC,s however, are still taking those components to the extreme. “It’s a matter of degree,” Bohr said.

      Indeed, Intel’s SoC is almost identical to its CPU version in terms of structure, including only some “minor tweaking” to provide either the lower leakage or higher volatage. It could even be described as a “superset” of the CPU version with expanded features.

      The SoC and CPU versions share many of the same process features; the same transistor structure and pitch along with similar interconnect and fab process equipment. “These two technologies can be run side by side in the same factory,” said Bohr, noting that all the yield learning for Ivy Bridge had been translatable.

      Bohr acknowledged that SoCs had presented Intel with new challenges. “When you talk about leakage, once you get down into the below 30 pico amp range, you have to deal with multiple sources of leakage, whether it’s through the gate oxide or leakage from source to drain or leakage from the drain to the substrate,” he said, adding that it had taken a lot of “tweaking an balancing” to finally get it right.

      The turning point had finally been reached, he said, with the firm’s 32-nm Medfield SoC. “You’ll see some pretty impressive SoC products coming next year on the 22nm generation,” he said.

      In terms of how Intel’s 22-nm SoC process stacks up against the 28-nm low power or forthcoming 20-nm processes from TSMC, Bohr claimed Intel had “far surpassed” the performance and low leakage capabilities of competitors. “We have a significant lead over our competitors,” he asserted.

      Intel is also banking on he new technology process having a long tail. “We know that it’s scalable to 14-nm,” he said, concluding that tri-gate was not only a big power advantage for Intel’s CPUs, but for other low power SoCs.

 
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