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Intel Corporation Message Board

  • semi_equip_junkie semi_equip_junkie Jan 12, 2013 12:20 PM Flag

    They finally figure it out - about to hit the fan

    But if wafers end up costing twice as much because double patterning — the application of multiple additional “mask layers” — is needed to get to smaller geometries, than the additional cost may outweigh any benefits.
    They finally figure it out - for a long time I predicted margins for fabless will come down
    the about to hit the fan

    East sems to be completely disconnected to what the foundries are doing - couple months ago East said Intel has no advantage in process technology for mobile ICs, says ARM CEOIntel ....BUT
    "We’re supporting all the independent foundries," says East. That includes 20nm planar bulk CMOS and 16nm finfet at TSMC; 20nm planar bulk CMOS and 14nm finfet at Samsung and 20nm planar bulk CMOS, 20nm FD-SOI and 14nm finfet at Globalfoundries.
    What a dork

    “The only benefit of a new geometry is to get more chips out of a wafer,” adds East.

    Just google DDR4 for example - what are the benefits of DDR4 for example for data centers?
    20% reduction in power requirements

    NVDA calls for 450mm wafers and they (TSMC, Samsung) all follow Intel investing in ASML/litho - I suppose GF is out of spare cash

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