We'll have to wait and see.
Do we? 12 months ago ....looks like TI's chip has all the bells and whistles
Fabbed in UMC's 28LP process, it utilizes two ARM Cortex A15 cores, and two low-power Cortex-M4 processors (taking the "big-little" approach discussed at the ARM Techcon last year). It has 2 MB cache, and the graphics side is covered by dual POWERVRÃ¢Â¢ SGX544-MPx graphics accelerators.
I would like to see how the cache works plus instruction retirement, flushing and delegation on two different cores trying to run a thread. How will both different cores handle the thread moving from one core to another. From what I heard, some software reprogramming is required to make use of both cores. Also interrupts and traps are going to be complicated. What happens if an interrupt occurs (e.g. from an I/O device) before the core change? What would happen to the interrupt routine if the core changes?