in SF. Free lunch ? Don't party too hard and perhaps someone can explain to you the difference between front end (transistor engineering) and back end (interconnects).
BTW do you know a guy by the name of Handel Jones.
He claims planar 20nm FDSOI (as proposed by STM) is 50 to 60% less expensive to 14/16nm FinFet ...are Samsung and Glofo betting on the wrong horse?
Also did they make up their minds about gate first or gate last?
I get the impression there's quite a bit of disarray in the ARM camp as we speak