Mentor moves tools toward 16-nanometer
8/23/2010 3:51 PM EDT
A conversation last Friday (Aug. 20) with Joseph Sawicki, vice president and general manager of the Mentor Graphics Corp.'s Design to Silicon Division, provided a snapshot of the conundra facing foundries and EDA vendors as they approach sub-20-nm process geometries. The landscape is filled with uncertainties, Sawicki warned, but there is no time left to wait for resolution.
"We saw our first 16-nm test chips go out a couple of months ago," Sawicki said in an interview Friday (Aug. 20). "There is design work going on now at that node—so far, though, it is mostly intellectual-property development."
Sawicki cited some big bets that foundries and design teams are being forced to put on the table. One is the choice of gate-first or gate-last processing for high-k/metal-gate gate stacks. "It seems clear that gate-first will provide greater density," Sawicki said, but he warned that other uncertainties remain, such as potential differences in process variations and even whether both approaches will scale below 20-nm.
The questions are critical to chip designers because the two major foundry powers—Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—have taken opposite approaches, leading them to have quite different design rules. Since there will not be easy portability between the two foundry groups, design teams may have to pick one track or the other.
There is also the still-unresolved lithography roadmap. Printers for critical layers at 16-nm might be EUV systems, or they might be massively-parallel e-beam direct-write systems. Or we might still be using 193-nm immersion lithography. Each choice requires different treatment of design data before the masks are made, and each would have different design rules.