A spokesperson for TSMC has told me that they won't be putting out any SEM cross-sections of the 16FF process until ICs made using the process have been sold.
Once that happens third parties can buy some chips, take a saw to a chip and take their own microphotographs. So TSMC may leave it up to those third parties or release some of their own.
well that was a response to EE - not me.
I like to see some more details about CSCO - in case it refers to Trigate (which I believe) it will be very telling.
Marketing works to some degree - but real data talks
Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor
the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module