Here in Titusville Joe is known as Joe "the Batman" Battapaglia. That reminds me: whatever happened to Mark Haines? He was the best guy on Squawk and then he just disappeared without a word. I kept expecting to show up on Fox Business or Bloomberg, but nothing so far.
"Here in Titusville Joe is known as Joe "the Batman" Battapaglia. That reminds me: whatever happened to Mark Haines? He was the best guy on Squawk and then he just disappeared without a word. I kept expecting to show up on Fox Business or Bloomberg, but nothing so far."
You are despicable, Hair Bawl Dooosh. You should be ashamed of yourself. Does your mother know the kind of filth you engage in every day? And, no, I don't mean the sewer pipes your actual business takes you into.
Intel will follow IBM's lead and IBIS makes the
Possibly before that chip is announced, IBM will start to
deliver a slower-speed PowerPC 750 to Apple that uses SOI
and the same process technology, he said. Each of the
SOI-based processors exhibit performance improvements over
previous-generation processors that are "greater than 30 percent,"
Meanwhile, IBM is now developing
its 0.18-micron- and 0.13-micron-generation SOI for
PowerPC chips. Shahidi said IBM plans to detail a 64-bit
device with a 1-GHz clock at the Hot Chips conference at
Stanford University in August, and may announce its
0.18-micron SOI process technology later this year at the
International Electron Device Meeting. The 1-GHz device will be
used in IBM's RS/6000 server series. The chip is
slated for introduction in 2001, and will go toe-to-toe
with Intel's McKinley processor, he said.
McKinley is expected to appear late in 2001. Initially,
Intel will use a 0.18-micron process technology, but is
expected to quickly migrate to a 0.13-micron process with
copper interconnects the following year.
able to cut channel-switching delay using SOI and
thereby boost chip performance significantly over its
current copper-based PowerPC chips that use bulk
technology. Shahidi said a ring oscillator circuit, a
benchmark widely used in the chip industry to measure
transistor speed, has delay of less than 10 picoseconds with
a channel length of 0.12 microns using a
0.22-micron CMOS process. That's comparable with transistor
speeds exhibited by Intel's 0.18-micron process based on
bulk CMOS, which uses shorter channel lengths because
of its smaller line widths, he said.
SOI technology employs a partially depleted insulator
that is about 1,000 angstroms thick, which is about
double the thickness of fully depleted material used by
other companies such as Motorola, he said. Shahidi said
there are several advantages to using partially
depleted devices compared with a fully depleted approach,
including the ability to use multiple threshold voltages,
better manufacturing characteristics and good
While IBM is moving forward, still others
are sitting on the fence. Samsung Electronics has
tested the waters by fabbing a 0.3-micron, 16-Mbit SOI
DRAM with a buried capacitor, and observed lower
operating current and a 27 percent power dissipation. But
there are many drawbacks to using the technology,
including a degradation of dynamic retention time,
uncertainty over floating-body effects, problems achieving
wafer uniformity, defects and price.
Samsung continues to press forward. "[SOI] still has many
advantages, and we're trying to minimize the problems," said
Jeong-Seok Kim, a researcher with Samsung Electronics.
Just as analog engineers are looking at SOI as a way
to isolate their designs from digital on the same
chip, it may also be useful for on-chip DRAM. "In
embedded DRAM, if you use a thick SOI layer you may have
good signal and thermal isolation from logic," said
Jeong-Mo Hwang from the R&D division at LG Semicon Co.