Wow. Big change in philosophy on Cadence's part - better analog kits and interoperable using OpenAccess. Should mean major changes in the analog design world.
TSMC unified iPDK works across multiple OpenAccess(TM)-based EDA design environments, eliminating the need for multiple proprietary PDKs, and enabling full reuse of design data between different custom IC design toolsets. The iPDK initiative is supported by all major EDA vendors including Cadence, Magma, Mentor, Springsoft, Synopsys, and others. The first iPDK in 65nm was developed in collaboration with TSMC development partners, Synopsys and Ciranova, and QA/validation partners, Magma and Springsoft. Its interoperable approach improves design accuracy, shortens design cycle times, promotes design reuse, and improves return on design investment.
SMC iPDK is based on the OpenAccess database and data model. It features open standard languages, Tcl and Python, for parameterized layout cells, callbacks, and technology files and includes unified views of symbols. The modern and flexible architecture easily accommodates specific customizations, future feature extensions and advanced and differentiated development. Customers will be able to extend the iPDK in the languages supported by the custom design tools of their choice. The iPDK also includes SKILL(TM) callbacks and component description format (CDF) files to provide compatibility with current OpenAccess-based PDKs and Cadence IC6.1 environment. TSMC continues to collaborate closely with key EDA partners to ensure full interoperability between the new TSMC iPDK and the currently available PDKs.
No, not a real change in Cadence's philosophy at all. Don't forget they introduced the OA database. But things aren't always what they seem. There is still a huge amount of things that are Cadence-specific-- things that PyCells fail miserably on. SKILL is far from dead, mon frere!!!
Also note that PyCells are nothing special... it's just a different way of doing things... not better, not worse, just differnt. Contrary to what Ciranova states, it isn't quite so easy to set them up to be DRC-correct... depending on the design rule set, it could take tens of thousand of lines to set things in place. On top of this, consider that when they say "correct by construction" they mean "lowest common denominator" of all the rules. Not exactly the best performance.
I work for a big TSMC+Cadence house, doing advanced-node designs (45nm and below).
We are excited about Pycells, are actively evaluating them, and already we see how much more productive we can be with them than with SKILL Pcells. Moving forward we will gradually move away from proprietary systems, and have all our designs based on modern, open standards.
I have seen correct by construction in PyCells that takes the complete deck for spacing rules for a 65nm. Definitely not the lowest common denominator. You should look more carefully at what they can do.
Also, tested optimized PyCells in several tools. Worked at least as good as SKILL pcells do in Virtuoso.
gippatel, can you be more specific as to how PyCell fails miserably for what it is INTENDED FOR?
Saying PyCells are nothing special is like sayng iPhone is just another cell phone. Yeah, I agree. Seems like you have been to Ciranova's website. Have you actually downloaded and used the production quality yet FREE PyCell developement system called PyCell Studio? I did. It even have a rather advanced PyCell demo library that actually comes with SOURCE CODES. Can I get SOURCE CODES from Cadence? Please?
Anyway, I urge anyone that wants to believe gippatel to go download that FREE PyCell Studio product and see for themselves how this PyCell thing is just another PCell and nothing special. I am sure the next thing is "FREE software! There must be a catch." The answer to it is already in their website.
Yeah, iPhone is just another cell phone. Don't buy it!