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Cadence Design Systems Inc. Message Board

  • Sentient_Cheeseburger Sentient_Cheeseburger Apr 7, 1998 11:09 AM Flag

    SOC

    Any body have any opinions about system on a chip (SOC)? (especially you engineers) With National's announcement about its
    upcoming microprocessor which it claims will drive PCs below $400, it seems SOC is the future. However, I've heard that it can be
    costly if one of the design models integrate onto the chip becomes out dated and slows the whole chip down - which can means new
    photomasks, which means new redesign adjustments, which means time-to-market delays, which could translate into millions (possibly
    billions if equipment issues arise) of dollars in delay costs.

    By the way, (as many of you probably already know) Cadence is a big proponent of SOC. In fact Cyrix, the microprocessor company which National (NSM) acquired and now is using to make its PC brains, used cadence design services on its line of x86 chips (and may still be using).

    Cheeseburger

    As an additional note, you might want to check out how well Unisys has turned around since it outsourced its chip design operations to Cadence. I know Unisys is primarily a systems integrator and therefore service oriented, but if the equipment is better...

    SortNewest  |  Oldest  |  Most Replied Expand all replies
    • Vitrual Sockets is an effort started in 94 trying to figure out a way to more quickly (and effectively) reuse IP blocks through a standard (or set of standards) for block interface. From waht I understand, it depends on quite a few changes in chip design orientation. Cadence kind of led the charge by spearheading the Virtual Socket Interface Alliance (VSIA). Take look at the article below.

      Cheeseburger

      http://www.cadence.com/features/vol3No1/todd_transition

    • Its an acroname for what happens all the time in processor design. More stuff gets pushed on the processor continuously. What you said about its surroundings become outdated would be true, but the main obstical to one processor forever is that the processor cant go faster im MHz than it was rated and sold at. At the rate processor speeds are increasing, that would be a fundamental problem. In 2 years when everyone is switching to 1GHz, who wants a 300MHz chip of today.
      The limitation of putting more and more system logic (all the other logic components in the box you buy) on the processor
      chip is often however the number of pins allowed on the package. You have to partition the system to have a minimal number of
      interface signals round each chip as the maximum can only be in the order of 400, given current and forseeable packaging technology.
      Most of these pins are memory related or bus interface related. The memory cant come onboard the chip as its much too big in
      silicon area. What can come onboard is some glue and specialist functions.
      The model you outline sounds like what has been happening more in embedded processing where a processor core has an
      application specific design incorporated into it. Of course if its requirements change then it needs another tapeout and product
      release. The good news is that the processor core (the thing that takes years to develop) is essentially the same, translating into
      faster time to market. You just change the bit specific to your system. ARM/SGS/LSI use this strategy very sucessfully and to some
      extent it goes on today at PC class processors from Intel/Sun/DEC etc.
      The difficulty with PCs is that the standard interfaces are fundamental requirements and often it makes sense to remove wide interfaces (which are relatively slow) from the core processor and put them on a shared high speed bust off chip to save IO pins.
      So in a nutcase, its what goes on is already happening to some extent in terms of leveraging from existing designs to get faster time to market but its not anything fundamental like one chip for life. Cadence helps by emphasising a design methodology using its tools to reuse blocks easier for faster turnround. As an aside its tools are better integrated that the competition so has a much better chance of doing this, but I'm biased.

      • 1 Reply to myoung4882
      • 4882,

        I know there's no such thing as the eternal chip or eternal processor core (especially with the proposed end of Moore's law
        approaching in the not to distant future), but my question revolved more around if it is more economically viable to redesign the entire
        IC with its SOC design because one of the blocks gets outdated, or just pop the problem chip out of the board and replace it
        with an updated one. Also, even if it is not as economically viable, is the increase in power (due to reduced distance) enough to
        justify the SOC design with all the risks of block obsoletion (is that a word?)? In addition, in reference to the connection issue,
        were you including flip chip/wafer bumping technology in your consideration when you mentioned "foreseeable pakaging
        technology"?

        Thanks for the info!

        Cheeseburger

 
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