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Cadence Design Systems Inc. Message Board

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  • san_jose_hockey san_jose_hockey Apr 5, 2001 3:10 PM Flag

    John Cooley is full of shit

    Cooley said otherwise in his tape-out count.

    "Concerning the newly crafted it's-not-a-tape-out-if-it's-not-full-P&R FUD
    coming from the "losers" (Cadence, Magma, Monterey), I'll defer to:

    "To claim 'tapeout' means that the tool was used in the design of
    a chip - nothing more. This applies to tools both in the early
    and late stages of a design flow. Whether GDSII is generated or
    not is of no consequence."

    - Michael Jackson, VP of Engineering, Avanti (EEdesign 12/15/00)


    As I stated at the beginning of this survey, although it may be impossible
    to follow the money in this contested market, tracking tape-outs will
    clearly show who's really ahead, who's really behind, and who's publicly
    lying because they're damn desperate in this market niche.

    In a nutshell, Synopsys, Cadence, and Magma are all claiming that they've
    made roughly $50 million in the physical synthesis market. But, when you
    look at the real customer tape-outs with these tools you'll find Synopsys
    has 65 vs. Cadence's 7 vs. Magma's 3 -- and Monterey has 0. From the
    outside looking in, Synopsys appears to be winning with by a 10X to 20X
    lead over Cadence and Magma -- and Monterey is in serious trouble.

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    • "To claim 'tapeout' means that the tool was used in the
      design of
      a chip - nothing more. This applies to tools both in the
      early
      and late stages of a design flow. Whether GDSII is
      generated or
      not is of no consequence."

      Bullshit. Many tools are used in the design of chip. If I use Chrysalis's Design Verify tool does that mean Chrysalis can claim a "tape-out".?

      Bet you were never an ASIC designer! And so is Cooley.

 
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