http://www.rambus.com/us/technology/innovations/serial_link/index.html For more than 20 years, Rambus has been a leader in serial link physical layer technology. Rambus pioneered the use of serial links in memory architectures and greatly advanced the use of serial link technology in communication interfaces. Rambus’ broad portfolio of patented innovations is fundamental to a wide range of industry standard serial links including PCI Express, Serial ATA, Serial Attached SCSI (SAS), DisplayPort and USB3.0. The serial link innovations available for licensing from Rambus include:
Transmitter Pre-emphasis and De-emphasis – Increases maximum operating frequency of a link by compensating for channel loss. Wide Frequency Range Phase Lock Loop (PLL) – Simplifies serial link implementations with continuous, wide-range frequency adjustment capability. Phase Interpolator-based Clock and Data Recovery (CDR) – Reduces cost, power, and area of a CDR circuit, and improves jitter performance in high-speed links versus PLL-based CDRs. Background
Wide parallel busses are frequently limited in their ability to scale to higher bandwidth and data rates due to intra-pair skew, crosstalk, other coupling impairments and physical limitations. Serial links enable greater scalability of performance by overcoming these pin and signaling limitations. Serial link technologies are sometimes referred to as SerDes which is an acronym for Serializer-Deserializer. The basic idea of a serial link is simple: parallel data (e.g. 8 bits wide) is Serialized (i.e. converted from parallel to serial), transmitted one bit at a time at a higher data rate which is proportional to the serialization ratio, and Deserialized (converted back to parallel from serial) at the receiver. For example, an 8-bit parallel bus operating at 100Mbps can be serialized into a 1-bit channel operating at 800Mbps.
Serialization allows for transmission of an equivalent amount of data over a narrower channel width by operating at a higher frequency thereby reducing pin count. Pin count reductions translate into smaller die and smaller packages (for both the transmitter and receiver). With fewer pins, connectors will be physically smaller and less PCB real-estate is consumed interconnecting devices and overall system cost is reduced.
Reducing the number of pins can also decrease the effects of crosstalk which leads to a more robust solution. However, since serial link architectures must operate at higher data rates, circuit design complexity increases. Rambus’ patented innovations in mixed signal circuits, packaging, and characterization techniques address the challenges of high speed serial link design and allow designers to harness all of the benefits of serial link technology.
In addition to Wide Frequency Range PLL, Phase Interpolator-based Clock and Data Recovery (CDR), and Transmitter Pre-emphasis and De-emphasis, serial link innovations available for licensing from Rambus include:
Clock Multiplying Delay Lock Loop (DLL) – Improves integration levels and noise rejection capability for high speed parallel and serial links. Partial Response Decision Feedback Equalization (PrDFE) – An equalization technology that allows receivers to capture data at multi Gigabit data rates even when the data eye at the receiver is completely closed. Data Filtering – A CDR technique that reduces jitter and provides more stable timing references. System Responsive Signaling – Optimized signal integrity can be achieved by configuring transmit levels and equalization settings as a function of the system configuration. Closed Loop Calibration – InSitu Signal Monitoring – Read link