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Rambus Inc. Message Board

  • exgeae exgeae Jul 24, 2012 11:23 AM Flag

    Rambus’ XDR™ Memory Architecture

    CoWare and Rambus Announce Unique ESL Architecture Design Environment for Rambus’ XDR™ Memory Architecture

    CoWare Solution Enables Design of Maximum Product Performance within Project Budgets

    SAN JOSE, CALIFORNIA, and LOS ALTOS, CALIFORNIA, - 02/09/2009 CoWare®, Inc., the leading supplier of platform-driven electronic system-level (ESL) design software and services and Rambus announced they have collaborated on a comprehensive ESL design environment with CoWare Platform Architect for Rambus’ XDR™ memory architecture. CoWare will distribute a SystemC model with the flexibility to match configurations of Rambus’ award-winning XDR memory subsystems.

    Design engineers can now use CoWare Platform Architect ESL environment to do full architectural exploration, design verification, and software performance validation when designing with an XDR memory subsystem. This solution provides a huge productivity boost for the design of high-performance systems by accelerating the design process as well as enabling parallel development of the hardware and software.

    Rambus’ XDR memory architecture transaction level model incorporates the XDR memory controller, memory controller interface (PHY), and XDR DRAM devices capable of delivering speeds of 3.2 to 4.8Gbps. The SystemC models allow thorough system performance analysis of various options for end applications, design configurations, and device types.

    “Optimum design of the memory and interconnect subsystem is important to help our joint customers achieve their overall design performance goals,” said Tom De Schutter, marketing manager, IP models, CoWare. “With today’s reduced design budgets, our customers have only one shot at their design goal. This development with Rambus enables customers to achieve their performance targets without going for a costly overdesign.”

    “CoWare’s ESL tools have been widely adopted for optimizing design performance on both the hardware and software levels,” said Tim Messegee, vice president of Marketing at Rambus. “The partnership with CoWare enables easy integration of our XDR memory architecture into the overall system platform and allows our mutual customers the full benefit of our XDR memory architecture.”

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    • Rambus and GLOBALFOUNDRIES Demonstrate Outstanding Performance and Power Results in 28nm Silicon Test Chips 07/24 03:30 PM


      SUNNYVALE, Calif. & MILPITAS, Calif.--(BUSINESS WIRE)-- Rambus Inc. (RMBS:$4.07,00$-0.09,00-2.16%) and GLOBALFOUNDRIES today announced the results from their collaboration on two separate memory architecture-based silicon test chips. The first test chip demonstrates solutions for mobile memory applications, such as smartphones and tablets. The second test chip demonstrates solutions for compute main memory applications, such as servers. Using GLOBALFOUNDRIES’ 28-nanometer super low power (28nm-SLP) process, and demonstrating the capabilities of one of the most power efficient and highest performance analog/mixed-signal offerings for advanced system-on-chip (SoC) developments, the results of the two test chips have surpassed power and performance expectations.

      “The partnership with GLOBALFOUNDRIES is vital to our ongoing commitment to innovation that advances the leading edge of electronics performance,” said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus (RMBS:$4.07,00$-0.09,00-2.16%) . “GLOBALFOUNDRIES’ 28nm-SLP process is ideal for achieving multi-gigahertz data rates at unmatched power efficiencies.”

      “Our 28nm-SLP technology gives SoC designers a robust manufacturing option for a new generation of feature-rich consumer and mobile devices, and assures optimal power consumption that is critical for success in these markets,” said Mojy Chian, senior vice president of Design Enablement at GLOBALFOUNDRIES. “We are pleased to be working closely with Rambus (RMBS:$4.07,00$-0.09,00-2.16%) to demonstrate the capabilities and design enablement ecosystem available for the industry’s most cost-effective and versatile 28SLP process.”

      Rambus’ mobile and server memory architectures are designed to meet the growing performance demands of future systems driven by applications such as 3D gaming, HD video streaming, capture and encoding, while providing unmatched power efficiency. With the rising popularity of streaming video, smartphones, tablets, and other smart mobile devices, there is a growing need for next-generation dynamic random access memory (DRAM) technologies capable of delivering the bandwidth necessary to power devices with the latest feature sets.

      GLOBALFOUNDRIES’ 28nm-SLP technology is designed specifically for the next generation of smart mobile devices, enabling designs with faster processing speeds, smaller feature sizes, lower standby power and longer battery life. The technology is based on bulk silicon CMOS substrates and utilizes the same “Gate First” approach to High-k Metal Gate (HKMG) that has reached volume production in GLOBALFOUNDRIES Fab 1 in Dresden, Germany.

      Over the past two years, Rambus (RMBS:$4.07,00$-0.09,00-2.16%) and GLOBALFOUNDRIES have collaborated on a number of 28nm-SLP test chips covering core Rambus (RMBS:$4.07,00$-0.09,00-2.16%) memory architectures for both mobile and server-based applications. The test chips leverage the wide range of design enablement support and solutions GLOBALFOUNDRIES offers, including process design kits (PDKs), extensive implementation services, and its DRC+™ design-for-manufacturing technology. Previously, Rambus (RMBS:$4.07,00$-0.09,00-2.16%) has also used the GLOBALFOUNDRIES assembly support team to provide wirebond and flipchip packaging options on high-speed PHY designs.

      More information on Rambus’ design implementation using the GLOBALFOUNDRIES 28nm-SLP process can be found in the companies’ 28nm collaboration white paper at:

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