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Cypress Semiconductor Corporation Message Board

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  • floppy_6 floppy_6 Jan 28, 2006 3:14 PM Flag

    Rosy Scenario - Some numbers

    Backlog is a whopping $700 millions.

    10% pricing premium than the peers due to higher conversion efficiency. Will reach 22% by the end of year while industry average is 15%.

    Wafer useage seems to drop to 8-9 gram/watt, competitive against the best - 8.5 from ESLR.

    Fails to elaborate why gross margin stays lousy - 19% compared against STP and Q-cell's 32%. Does 19% partly compensate the fab setup cost? How is the trend to improve it? SPWR didn't mention this crtical issue.

 
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