FinFET race holds promises, perils
3/27/2013 10:01 AM EDT
SANTA CLARA, Calif. – FinFETs hold both promise and peril and are not yet ready for prime time, according to a panel of experts who spoke on their experiences with the technology at the annual Synopsys User Group meeting here.
The 3-D transistor structures coming at the 14-nm node promise either performance increases or power consumption reductions of more than 60 percent compared to today’s 28 nm process, according to a Globalfoundries technical executive. However, they increase gate capacitance on a per micron basis, raising a handful of old and new design issues, said others on the panel.
FinFETs bring a 66 percent increase in gate capacitance per micron compared to today’s-28 nm process, back up to the level of the 130-nm planar node, said Anil Jain, vice president of IC engineering at Cavium Networks. Capacitance will limit both performance increases and dynamic power scaling for high-end chips, he said.
“We have these beautiful [3-D] transistors, but we can’t run them too far,” Jain said, noting “dynamic power [is] getting out of hand.” In addition, “those of us in high performance devices have not seen much improvement in core voltage scaling,” he said.
Jain asked EDA vendors for tools that do a better job controlling switching power and isolating electro-migration faults. “FinFETs are not a no-brainer migration--at the end of the day we have to pay for it, so please don’t blow up our costs,” he added.
Michael Campbell, a vice president of engineering in Qualcomm’s chip design group, said FinFET structures in one foundry are “similar, but not the same” as those in another foundry. “You can only etch in certain directions and etch tools are common—that drives some similarities--but [foundries] use different in tricks in spatial walls and diffusion,” he said.
Campbell noted pictures of Intel’s 22 nm FinFETs show irregularly tapered walls that could impact planar fault models. “It takes new test technologies and incredibly deep partnerships to do design for test properly,” he said.
Targeting chips in late 2014
In EDA, Synopsys “Yield Explorer is a great tool, but it still looks planar--it needs to evolve into a 3-D tool,” he said. “Tools from Synopsys and others are woefully lacking in compressing a simple ATE pattern that can step backwards to find faults,” he added.
Jain and Campbell both expect to see some of the first 14 nm FinFET chips hit the market in late 2014 if the current issues get addressed.
“I would say the processes are close to being ready but the design flows still need work,” said Campbell. “Today we build [14 nm FinFET] test chips with 20 million gates, but a commercial SoC may have is two billion gates,” he said giving one measure of the work ahead.
Joachim Kunkel, general manager of Synopsys’ IP core group, provided another snapshot of the progress to date.
His group taped out a 20 nm test chip in April 2012 that showed working MIPI, PCI Express and USB interfaces using double patterning. A follow up 14 nm chip was a simpler device mainly focused on memory, and has not yet come back from the fab.
The design parameters for FinFETs are very different from those of the planar nodes,” Kunkel said.
"The differences between the various FinFET processes available from the foundries today are significant enough that we have to start over [with IP development] each time," he said. "Also, most FinFET processes and design kits are still in the development phase, adding to the effort," he added.
FinFETs “will drive a complete re-evaluation of your architecture--how you separate out devices and optimize them—it’s a big change,” Campbell said.
and here's where the rubber meets the road - that's why Intel invested $ 4 billion into litho -
suddenly the ARM folks call TriGate / FF a no brainer; - pathetic
Intel always goes up on its own until some anals try to slam Intel stock
Only 717 received the transcript - no wonder the market is stupid
from ASML management presents at UBS technology conference...
The more you start to look into the details where an eagle is it looks like when you go to a 14-nanometer logic design, which they will call 10 or 11 or 9 in terms of nomenclature they also call 20-nanometer 16 and 14 and it’s one big mess in terms of how do you call it. But if you look at it in terms of lithography point of view, 14-nanometer lines which is the next generation. It comes after 20 is awfully, awfully difficult in double-patterning left below multiple-patterning and if at all you are able to do it, you are imposing yourself a lot of design restrictions, limitations and also at significant higher cost.
Nevertheless, “the whole industry is trying to pull in the first generation of FinFETs in terms of time to volume,” said Subramani Kengeri, vice president of design solutions at Globalfoundries.
In the race to catch up with Intel’s 22 nm FinFET process, now in production, foundries have agreed to take two separate steps, he said. First they are tackling at 20 nm the need for double patterning with 193-nm lithography. Then they are adding 14 nm FinFETs as “front end” devices in a node that still uses 20 nm “back end” interconnects, he said.
Kyu-Myung Choi, senior vice president of Samsung’s infrastructure design center for logic, reiterated the Korean giant’s promise to have a 14 nm FinFET process ready for “risk production” by the end of 2013. Both Choi and Kengeri said work on the 14 nm node is on track in terms of yields and performance.