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Intel Corporation Message Board

  • semi_equip_junkie semi_equip_junkie Jan 2, 2013 11:40 PM Flag

    20nm planar node - “negative ROI.” ?

    As already posted 20nm litho cost is going to increase by 1.7 compared to 28nm.
    Good chance Apple could end up with a 20nm lemon -
    ASML made a new all time high - LRCX (one of the leader in double patterning up 7%) -
    "ARM chip analysts" are completely clueless when it comes to economics - Hans Mosemann is aprime example

    Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

    Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

    The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

    IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

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