I'm starting to challenge my own investment in Intel. Even if they start capturing the tablet and phone market, it will need to be at lower price points which will still canabolize core i products. They will really need to have a value proposition in their SOC offering such as WIDI, power savings, interfaces etc. They could possibly have the entire silicon in the SOC (flash,camera,touch controller,memory,usb,wifi,4G and GPS).
"There isn't just one version of our SoC technology," Bohr said. "We [will] offer a rich menu of options to pick and choose from, both different transistor options and different interconnect options," said Bohr.
Why FinFET is good for analogue design
Bohr said it was now abundantly clear that 22nm tri-gate SoCs outperformed 32nm planar devices by a margin of 20 to 65 per cent, while covering four different orders of magnitude in current leakage.
Intel said its 22nm tri-gate product also exhibits superior short channel control, with optimum sub-threshold slope and drain-induced barrier lowering (DIBL). The sub-threshold slope allows for low leakage but could also function well at low voltage, making them "much better than the very best planar devices," Bohr added.
Bohr said the low numbers for DIBL seen in testing were a measure of good performance in short channel control, with the new SoC pulling in DIBL numbers of 30 to 35mVs, while comparable products had DIBL's closer to the 100mV range.
Bohr said that when Intel had first announced it would be using tri-gate devices, other companies had argued that FinFET transistors would not aid analogue design. "Well, they're wrong," declared Bohr.
For analogue designers, he asserted, an important transistor metric is transconductance by power out (GM x Rout). Bohr said that while this value had been steadily degrading over the past few generations, it had shot up again in 22nm tri-gate SoCs, making it easier for analogue circuit designers to use than Intel's previous three generations of planar technology.
Bohr also touted the technology's advanced passive features, including precision resistors, MIM capacitors and high Q inductors.
You are EXACTLY right on the cannibalization point. I have been saying the same thing for eight years.
INTC resisted doing SOCs for years because it is the beginning of the end for margins. They preferred selling you at least three chips with 40% markup on the CPU and probably 3x that on the south bridge.