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Intel Corporation Message Board

  • semi_equip_junkie semi_equip_junkie May 15, 2013 10:12 PM Flag

    FinFETs still not ready for prime time

    Opinions/concerns expressed by ARM eco system
    The consensus among participants at the annual Synopsys User Group meeting is that FinFETs hold both promise and peril and are not yet ready for mainstream use.

    The 3D transistor structures coming at the 14nm node promise either performance increases or power consumption reductions of more than 60 per cent compared to today's 28nm process, according to a Globalfoundries technical executive. However, they increase gate capacitance on a per micron basis, raising a handful of old and new design issues, said others on the panel.

    FinFETs bring a 66 per cent increase in gate capacitance per micron compared to today's 28nm process, back up to the level of the 130nm planar node, said Anil Jain, vice president of IC engineering at Cavium Networks. Capacitance will limit both performance increases and dynamic power scaling for high-end chips, he said.

    "We have these beautiful [3D] transistors, but we can't run them too far," Jain said, noting "dynamic power [is] getting out of hand." In addition, "those of us in high performance devices have not seen much improvement in core voltage scaling," he said.

    Jain asked EDA vendors for tools that do a better job controlling switching power and isolating electro-migration faults. "FinFETs are not a no-brainer migration—at the end of the day we have to pay for it, so please don't blow up our costs," he added.

    Michael Campbell, a vice president of engineering in Qualcomm's chip design group, said FinFET structures in one foundry are "similar, but not the same" as those in another foundry. "You can only etch in certain directions and etch tools are common—that drives some similarities—but [foundries] use different in tricks in spatial walls and diffusion," he said.

    Campbell noted pictures of Intel's 22nm FinFETs show irregularly tapered walls that could impact planar fault models. "It takes new test technologies and incredibly deep partnerships to do design for test properly," he said.

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    • In EDA, Synopsys "Yield Explorer is a great tool, but it still looks planar—it needs to evolve into a 3-D tool," he said. "Tools from Synopsys and others are woefully lacking in compressing a simple ATE pattern that can step backwards to find faults," he added.

      Jain and Campbell both expect to see some of the first 14 nm FinFET chips hit the market in late 2014 if the current issues get addressed.

      "I would say the processes are close to being ready but the design flows still need work," said Campbell. "Today we build [14nm FinFET] test chips with 20 million gates, but a commercial SoC may have is two billion gates," he said giving one measure of the work ahead.

      Joachim Kunkel, general manager of Synopsys' IP core group, provided another snapshot of the progress to date.

      His group taped out a 20nm test chip in April 2012 that showed working MIPI, PCI Express and USB interfaces using double patterning. A follow up 14nm chip was a simpler device mainly focused on memory, and has not yet come back from the fab.

      "The design parameters for FinFETs are very different from those of the planar nodes," Kunkel said.

      "The differences between the various FinFET processes available from the foundries today are significant enough that we have to start over [with IP development] each time," he said. "Also, most FinFET processes and design kits are still in the development phase, adding to the effort," he added.

      FinFETs "will drive a complete re-evaluation of your architecture—how you separate out devices and optimise them—it's a big change," Campbell said.

      Nevertheless, "the whole industry is trying to pull in the first generation of FinFETs in terms of time to volume," said Subramani Kengeri, vice president of design solutions at Globalfoundries.

      • 1 Reply to semi_equip_junkie
      • In the race to catch up with Intel's 22nm FinFET process, now in production, foundries have agreed to take two separate steps, he said. First they are tackling at 20nm the need for double patterning with 193nm lithography. Then they are adding 14nm FinFETs as "front end" devices in a node that still uses 20 nm "back end" interconnects, he said.

        Kyu-Myung Choi, senior vice president of Samsung's infrastructure design centre for logic, reiterated the Korean giant's promise to have a 14nm FinFET process ready for "risk production" by the end of 2013. Both Choi and Kengeri said work on the 14nm node is on track in terms of yields and performance.

        - Rick Merritt
        EE Times

        Another excellent article was published by SemiMD:
        Top Five Design and Manufacturing Challenges at 20nm .

        keep in mind Intel processed megatons of TriGate silicon - that's how complex and complicated technology gets "debugged" -
        Intel published a paperon reliability issues in regards to FinFet/TriGate - NOBODY in the world has this kind of info - a nice leverage to pick some foundry customers

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