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Intel Corporation Message Board

  • ossobucco2012 ossobucco2012 Jul 27, 2013 8:13 PM Flag

    Intel has developed 10 nm technology....

    Folks as we approach the product release for the 14 nm class, as I pointed out in my earlier post, the new Arizona and Oregon facilities are built to go beyond 14 nm and 10 nm is the next one up....

    The product launch date will be 2016 as by that time Intel 14 nm will fully destroy ARMH and QCOM et al.


    Sentiment: Strong Buy

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    • bump

    • ARMH + QCOM + Samsung + TSMC = AMD = DEAD


      Sentiment: Strong Buy

    • They will pretty much amount to low end market plays, that's for sure.
      I'm pretty sure as well that Intel will reach $30 after Baytrail and Merrifield are in full force. About the time of the 2014 Mobile World Congress, when new and popular smartphones will come with Intel processors.

      Sentiment: Strong Buy

    • Link? Proof? Pump and Dump?

      • 1 Reply to letstalkintc
      • The 10 nanometer (10 nm) node is the technology node following the 14 nm node. By the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm, although Intel's Architecture and Silicon Cadence Model places its 10 nm node closer to the year 2015. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, pointed out in 2008 that Intel sees a 'clear way' towards the 10 nm node. At the 11 nm node in 2015, Intel expects to use a half-pitch of around 21 nm.

        However, in 2011, Intel updated its plans to suggest skipping 11/10 nm and going directly to 8 nm in 2015.

        While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Reported estimates indicate that transistors at these dimensions are significantly affected by quantum tunnelling. As a result, non-silicon extensions of CMOS, using III-V materials or nanotubes/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics. Quantum tunneling may not be a disadvantage when its effect on device behavior is fully understood and used in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible.

        Sentiment: Strong Buy

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