During the trial, it was discovered that Intel had an internal roadmap which was moving away from RDRAM, and was forced to display an external roadmap due to arbitration while trying to cut ties with Ramscam.
I thought you were paying attention to the trial, or are you only looking for facts which bolster your beliefs?
You mischaracterize what "Intel said." During the trial, the cartel produced two former low level Intel employees who spoke of an internal Intel roadmap. Intel is a very large organization with a lot of employees, not all of whom have the same opinions about techology and the way Intel should go. Just because two low level former employees did not like Rambus and imagine that Intel was lying to the world about it's intentions surrounding RDRAM doesn't make it so.
I just provided what "Intel said", from the very top of the organization. Want more? Here's what Pat Gelsinger, Intel's former VP of Desktop Products said at the 2000 Intel Developer Forum:
"We're not changing our memory strategy. We need a next generation technology and the best way to accomplish that is RDRAM (Rambus memory). He said that Intel was incorporating two channels of Rambus memory into its future chipsets to emphasise that. "Our roadmap is not very different from what it was before," he said. "We'll ship multi millions of i820 [chipsets] in the next quarter, and some of these will be in two + two configurations, mixing synchronous memory and Rambus memory." That confirms our earlier story of a new rev of Caminogate which combines the two disparate memory standards. He said: "We do expect that the launch of RDRAM into the value sector will be longer and slower than we thought." The introduction of technology such as Willamette needed two channels of such memory to be able to deliver speeds in excess of 3GHz per second, he said. "We are not deploying or building products that use DDR in the mobile or desktop space. It [DDR] is too late, too little, it doesn't work and it doesn't fit in the desktop,"
Obviously, Intel had an internal roadmap, otherwise they would not have had SDRAM version of the P4 processor out so quickly in 2001. I would argue that engineers know better than execs when it comes to the technology, so quit marginalizing them as "low level", it's demeaning.
A Hz by definition is # cycles per second, so saying "3GHz per second" is redundant. Obviously, the "low level" engineers understand this better than Pat Gelsinger, so you should take any technical jargon this guy spews with a pound of salt.
How many freaking times does it need to be said that bandwidth does not equal performance, you keep touting the bandwidth crap as if it matters, when we all know that latency on RDRAM was 3x SDRAM, which made it slower for every day computing.