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QuickLogic Corporation Message Board

  • pivot_finder pivot_finder Jul 9, 2013 6:58 PM Flag

    Interview with Andy Pease

    Google: Maverick or visionary? Interview with Andy Pease, president and ceo, QuickLogic

    Sentiment: Buy

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    • Andy Pease tells Caroline Hayes his company's focus on programmable logic in the mobile market is the right path – whatever competitors do.

      There is no doubt the programmable logic market is evolving, but while the leading companies push towards the lowest process node, QuickLogic is marching to the beat of a different drum. Its portfolio is largely based on 180nm technology – although the latest ArcticLink III VX is a 65nm part – but insists that is not holding the company back. It distances itself further from Altera and Xilinx as it transitions from being an fpga supplier to a supplier of customer specific standard products – or cssps.

      It is a risky strategy: cssps are targeted at price conscious mobile and consumer markets, where margins are lower than those of fpgas. Pease refused to be goaded when asked if there is still a place for assps. "Do you know how large the programmable logic industry is? $3billion. The market is growing and assps are growing. I certainly agree that asics are dead, but assps? Really?"

      The company is transitioning from being a broad based fpga supplier. Target markets are portable computing, smartphones and mobile internet devices, as well as broadband data cards, mobile enterprise and personal media players, and portable navigation devices.

      "Here is a fundamental truth that we fight all the time – why do you have fpgas?," he asked. "Because they are flexible, but the cost is obscenely high. The development cost for a 28nm chip may be $20million. And here's another truth they don't talk about – it's eye popping the space it takes to put in a given function in programmable logic versus putting it in a standard cell or assp technology." Warming to his theme, he issued a challenge: "What do you think the size penalty is?" Without waiting for an answer, he declared: "You can put 10 times as much in a standard cell as you can in programmable logic. The things we put into a standard cell are things you cannot do in programmable logic;

      • 1 Reply to sethbru2
      • any analogue or mixed signal, MIPI, USB – all need a standard cell component."

        Quicklogic put the full algorithm for VEE (Visual Enhancement Engine) and DPO (Display Power Optimiser) in its ArcticLink chip; the earlier PolarPro could only accommodate part of the algorithm. It also took x10 less space, leaving room for more fabric. Pease enthused: "We added a full MTDI interface; we even put a frame buffer in the interface and the resulting chip was smaller. The whole point of ArcticLink is to have some programmable logic and, in the mobile space, we have to be very, very cost effective."

        Pease knows programmable logic; he worked at Vantis, AMD's programmable logic spin off. He estimated that, in 2000, fpgas were 45% of the programmable logic market. Today, he estimates 75 to 80%, dominated now, as then, by Altera and Xilinx. So where does QuickLogic fit?

        He whips a business card from his jacket's inside pocket. It is from the early days of the company and bears the Via Link logo, similar to the Jedec symbol. "I keep this as a 'show and tell'," he confides. "Via Link [the company's metal to metal technology] is non reprogrammable; the rest of the industry's is reprogrammable. They have static ram cells – if you take power from the static memory, the cell becomes blank."

        What could have been a technology that pigeonholed the company into high end applications has become a differentiator. Just as the company was pondering how it could take its programmable logic, which could differentiate hardware, into a space where Altera and Xilinx were not, 'the mobile market popped up', said Pease. "The cool thing about [it] is that every metal to metal connection is a possibility. It is much more dense and, once you have made the connection and turn off the power, the connection is still there, so static power is minuscule.

        "With fpgas, you need code for the algorithm to be stored in either a separate on chip memory or on a prom. But you need to boot these; there is no

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