you're too dumb to google....it's all about mobile
Altera Corporation today announced that NEC will use Altera’s 28 nm FPGAs to bring new levels of performance to its Long-term Evolution (LTE) base stations and enable wireless service providers to more effectively manage their networks.
Altera Stratix® V and Cyclone® V FPGAs drive the complex algorithms that allow NEC’s LTE base station infrastructure offering to improve operators’ data performance while lowering investment and operation cost of the network.
Featured report: Global Semiconductors for Wireless Communication Devices Market 2012-2016
“Wireless providers moving to LTE continue to seek ways to more efficiently deploy and manage their networks,” said Mr.Nozomu Watanabe, General Manager, Mobile RAN Division, NEC. “Altera’s 28 nm portfolio will enable us to innovate on our base station architecture which operators can use to superior services to users while reducing capital costs and operating costs.”
Altera’s 28 nm FPGAs provide the flexibility and performance needed to implement the various LTE system level features of the next-generation base station without sacrificing power efficiency.
LTE enables improved wireless service to users, allowing multitude types of services to be offered, enhancing users’ mobile experiences. It also allows operators to utilize bandwidth more effectively because it supports network deployment on different frequency bandwidths.....blah, blah, blah
AMSTERDAM (AP) -- Shares in ASML Holding NV surged Tuesday on news that Intel Corp intends to take a 15 percent stake in the company for around $3.07 billion, and will also help fund its research into new technologies. ASML said other large customers may also take equity stakes.
Shares closed up 8.6 percent at #$%$43.15 ($53).
though at smaller scale Intel has been in FPGA -besides ALTR - for a long time.
Yes Cramer is trying hard - only morons follow charts when it comes to chip equipment.
When Cramer hates one should love -
INTC runs this company for the benefit of management, not the stockholders.
did you ever get stock options?
do you follow "insider selling"
do you follow the chart?
This is my chart. There are many like it, but this one is mine.
My chart is my best friend. It is my life. I must master it as I must master my life.
Assuming our estimates are correct, the co-packaged 128MB eDRAM for Haswell will probably be 70-80mm2 (suggesting that the GT3e Haswell variant is around 210-240mm2). The embedded DRAM data arrays alone are at least 60mm2, and that doesn’t include overhead such as the controller and physical layer interfaces to the host SoC. Intel is rumored to be selling this part for around $50, which should give margins similar to low-end or mid-range client SoCs. While the price is less than a comparable-sized SoC, the cost should be lower since fewer layers of interconnect are needed. Conceptually, it will increase Intel’s manufacturing volumes and fab utilization without substantially sacrificing margins. As an added benefit, Intel’s integrated graphics will become much more robust and competitive.
In this regard, Intel is living up to its name and simply integrating more of the PC platform. While this is not competition for any DRAM vendors, it is an indirect threat. As Intel’s integrated graphics becomes more capable and takes more of the market, DRAM consumption will shift from companies like Nvidia and AMD (which buy from Samsung, Hynix, Micron, etc.) to Intel.
To put this in perspective, Intel has compared the Haswell GT3e performance to the discrete Nvidia GT 650M, which is used in the 15” Macbook Pro with 1GB of GDDR5. The GT 650M can also be configured with 2GB of DDR3 and is used by many other OEMs including Lenovo, Asus, and HP for notebooks that are priced around $1000. Intel’s 128MB custom eDRAM solution has similar bandwidth, but lower power and less board area, thus reducing the demand for GDDR5/DDR3 by supplanting it with Intel’s custom silicon.
Intel’s return to the DRAM business is emblematic of a larger shift in the industry. Moore’s Law is alive and well, but improving performance requires more than just shrinking transistors. Intel’s strategy is quite clear: differentiate through superior process technology and manufacturing and leverage this advantage through greater integration and delivering higher performance to customers. Intel’s embedded DRAM is just one step in this direction, there are assuredly many others on the roadmap.
Not so much about NAND
Intel’s Long Awaited Return to the Memory Business
April 23, 2013 by David Kanter
.....if you like to read google it - Mars once mentioned David Kanter - opposite to G61 I don't suffer from memory loss....
Intel’s Embedded DRAM
Embedded DRAM has a long history of niche applications within the industry. The biggest proponent by far is IBM, which uses eDRAM for the massive last level caches in the POWER7, POWER7+ and z196 server processors to improve array density. A more widespread application is the high bandwidth framebuffer in the Xbox360. At IEDM 2010, IBM reported results for eDRAM on a 32nm SOI process.
The VLSI paper from Intel describes a good implementation of embedded DRAM, particularly for a first generation product. While some of Intel’s reported metrics are less impressive than what IBM has achieved, Intel has only entered the field and is also constrained by cost-conscious customers.
Intel uses a trench capacitor to store the actual data bits. Unlike IBM’s work where the trench is dug into the silicon substrate, Intel’s eDRAM forms a high aspect ratio trench above the transistors in the metal interconnects and interlayer dielectrics and filled with a metal-insulator-metal capacitor. Presumably this improves manufacturing flows and yield at the cost of performance. The access transistor which controls the capacitor is one of Intel’s novel 22nm FinFETs to reduce leakage, which is crucial in determining retention time....
While Intel’s eDRAM will have a big impact on the industry, it is not a direct threat to the high volume vendors like Samsung or Micron. The DRAM business is mostly a low margin, commodity business where cost metrics drive decisions; there are a few exceptions such as specialized solutions for high value applications such as networking or graphics
. I think a better question might be ...
the "holy grail"....it's not only about shrinking...
this blurb is about 2 years old...
We've known for a while now that Intel will integrate some form of DRAM on-package for the absolute highest end GPU configurations of its upcoming Haswell SoC. Memory bandwidth is a very important enabler of GPU (and multi-core CPU) performance, but delivering enough of it typically required very high speed interfaces (read: high power) and/or very wide interfaces (read: large die areas). Neither of the traditional approaches to scaling memory bandwidth are low power or cost effective, which have kept them out of ultra mobile and integrated processor graphics.
The days of simple performance scaling by throwing more transistors at a design are quickly coming to an end. Moore's Law will continue but much like the reality check building low power silicon gave us a while ago, building high performance silicon will need some out of the box thinking going forward.
Dating back to Ivy Bridge (3rd gen Core/2012), Intel had plans to integrate some amount of DRAM onto the package in order to drive the performance of its processor graphics. Embedding DRAM onto the package adds cost and heat, and allegedly Paul Otellini wasn't willing to greenlight the production of a part that only Apple would use so it was canned. With Haswell, DRAM is back on the menu and this time it's actually going to come out. We've referred to the Haswell part with embedded DRAM as Haswell GT3e. The GT3 refers to the GPU configuration (40 EUs), while the lowercase e denotes embedded DRAM. Haswell GT3e will only be available in a BGA package (soldered-on, not socketed), and is only expected to appear alongside higher TDP (read: not Ultrabook) parts. The embedded DRAM will increase the thermal load of the SoC, although it shouldn't be as painful as including a discrete GPU + high speed DRAM. Intel's performance target for Haswell GT3e is NVIDIA's GeForce GT 650M.
To answer your Question - yes Toshiba announced as well
some people are really upset about copy and pasting ...but what's the problem....first you need to look where...I think for Enterprise reliability is important - wasn't that one of the reason for SLC.
Micron bought the NOR bizz from Intel - if IMF could expand beyond NAND they could bundle a lot just like Samsung .
Bundle NOR, NAND and LPDRAM plus APU -
Samung is already doing it
from ANANDTECH today
That said, Intel-Micron did disclose that their design utilizes a traditional floating gate, whereas the other 3D NAND designs we have seen use a newer charge trap technology. There's inherently several benefits to charge trap (e.g. less electron leakage), but Intel and Micron told me that they decided to use floating gate because it's a decades old design and the physics are well known, while charge trap is much newer and more unproven. It's impossible to outright say that one cell structure is better than the other because in the end it all boils down to cost where floating gate design is probably more cost efficient for Intel-Micron given their deep knowledge of its functionality.
Innovative Process Architecture
One of the most significant aspects of this technology is in the foundational memory cell itself. Intel and Micron chose to use a floating gate cell, a universally utilized design refined through years of high-volume planar flash manufacturing. This is the first use of a floating gate cell in 3D NAND, which was a key design choice to enable greater performance and increase quality and reliability.
The new 3D NAND technology stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package. These capacities can enable gum stick-sized SSDs with more than 3.5TB of storage and standard 2.5-inch SSDs with greater than 10TB. Because capacity is achieved by stacking cells vertically, the individual cell dimensions can be considerably larger. This is expected to increase both performance and endurance and make even the TLC designs well-suited for data center storage.
OMG... a floating gate ....before "opening" the doors to NVDA Intel would be better off revisiting memory lane (next to semiconductor drive)...in particular there is a trend to bundle NAND and LPDRAM ....or even APU (in case of S
This new 3D NAND technology, which was jointly developed by Intel and Micron, stacks layers of data storage cells vertically with extraordinary precision to create storage devices with three times higher capacity than competing NAND technologies. This enables more storage in a smaller space, bringing significant cost savings, low power usage and high performance to a range of mobile consumer devices as well as the most demanding enterprise deployments.
Planar NAND flash memory is nearing its practical scaling limits, posing significant challenges for the memory industry. 3D NAND technology is poised to make a dramatic impact by keeping flash storage solutions aligned with Moore’s Law, the trajectory for continued performance gains and cost savings, driving more widespread use of flash storage.
“Micron and Intel’s collaboration has created an industry-leading solid-state storage technology that offers high density, performance and efficiency and is unmatched by any flash today,” said Brian Shirley, vice president of Memory Technology and Solutions at Micron Technology. “This 3D NAND technology has the potential to create fundamental market shifts. The depth of the impact that flash has had to date—from smartphones to flash-optimized supercomputing—is really just scratching the surface of what’s possible.”
“Intel’s development efforts with Micron reflect our continued commitment to offer leading and innovative non-volatile memory technologies to the marketplace,” said Rob Crooke, senior vice president and general manager, Non-Volatile Memory Solutions Group, Intel Corporation. “The significant improvements in density and cost enabled by our new 3D NAND technology innovation will accelerate solid-state storage in computing platforms.”
this was one day before "DRAM weakness"
I believe there was massive shorts piling into LRCX specifically and than dragging the whole group down - nothing new
North American Semiconductor Equipment Industry Posts February 2015 Book-to-Bill Ratio of 1.02
SAN JOSE, Calif. — March 19, 2015 — North America-based manufacturers of semiconductor equipment posted $1.31 billion in orders worldwide in February 2015 (three-month average basis) and a book-to-bill ratio of 1.02, according to the February EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.
The three-month average of worldwide bookings in February 2015 was $1.31 billion. The bookings figure is 1.3 percent lower than the final January 2015 level of $1.33 billion, and is 1.0 percent higher than the February 2014 order level of $1.30 billion.
The three-month average of worldwide billings in February 2015 was $1.28 billion. The billings figure is 0.2 percent lower than the final January 2015 level of $1.28 billion, and is 0.9 percent lower than the February 2014 billings level of $1.29 billion.
"Year-to-date bookings and billings for North American semiconductor equipment are higher than last year for the same time period," said SEMI president and CEO Denny McGuirk. "The year is off to a good start, with growth in bookings from the back-end sector.”
The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.
It's coming faster than expected - might to relocate more to intel
To offset the weak demand for 20nm, TSMC has pulled forward 16nm to 2Q by offering significant price concession to entice Apple for a larger allocation of A9 orders. TSMC’s 16nm wafer ASP is now on par with its 20nm and Samsung’s 14nm level. In respond, Samsung will offer Apple a package deal by combining mobile DRAM, high density NAND, A9 AP and PoP packaging. The competition is indeed keen.