comes from an idiot who yesterday claimed that e ASIC would replace FPGA -
comes from the nut case who floated the rumor ALTR would be dumping Intel -
you're loose canon -
The next big #$%$ to improve overall system performance will be stacked memory connected via TSV - TSV is the next big driver for equipment "people" LRCX in particular.
Intel already implemented this technology in high end server chips -
the main culprit is cost - according to Bohr - so IMO it's strictly a manufacturing / cost issue and Intel is good in this area
Nowhere in the press release does it say
Why would they tell you....?
And e ASIC won't put ALTR nor XLNX out of business
did you notice how Samsung and TSMC gloat about their technology while Intel maintains a low profile?
Intel is not ARM's largest customer. Wow, not even close. Pot is legal in your state?
do I care - not at all as long as Samsung and TSMC keep spending I am happy -
many of TSMC customers who used to upgrade to new technology won't - they will stick with 28nm trying different ways to improve it - TSMC will be forced to spend time and capex on "older" technology -there is only one left and that is Apple who will play Samsung against TSMC
eASIC and ARM have a long standing relationship so nice try.
so what ?
and isn't Intel ARM's largest customer?
An ASIC is less expensive compared to an FPGA which is flexible compared to ASIC.
Cost versus flexibility ....with eASIC Intel covers its server ground ....regardless of ALTR Intel has already exposure to FPGAs
I think ASML's plate is more than full
the LRCX & NVLS merger was perfect because both complemented each other 100% -
my guess is as good as yours
Moore’s Law to keep on 28nm
Solid State technology - good article
Dimensional scaling below 28nm will only increase the ‘component cost’ as we described in Moore’s Law has stopped at 28nm and is detailed in the following tables published recently by IBS.
(not for Intel)
“Device and circuit cleverness” as a factor will never stop; however, it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D.
And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore’s Law to last another 10 years” Bohr is quoted predicting “that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”
Intel has integrated a new form of stacked memory based on Micron’s Hybrid Memory Cube technology, which provides 15 times more bandwidth than DDR3 DRAM and five times more throughput than the emerging DDR4 memory. The new memory technology consumes three times less space and five times less power than DDR4, Hazra said.
Knights Landing has 16GB of the new memory type, which should be key in speeding up supercomputing applications, Hazra said. The modules on the board have stacked memory chips linked through a wire-like connection called Through Silicon Via (TSV), which brings performance advantages.
Embedded on the supercomputing chip is DDR4 memory, which can be used as cache or conventional system memory for less-demanding applications.
There is a BIG difference ....Zweistein
Intel runs megatons of Trigate silicon with excellent margins and yields ....10nm will be third generation
still waiting for chipworks complete teardown of Samsung FinFet although the promised months ago
TSMC and Samsung transparency with regards to FinFet is as clear as mud
does Samsung break down its revenue/profits according to NAND, DRAM and logic?
ARM attempts to crack the server market only motivates Intel more ....see eASIC announcement
Application Specific IC
eASIC’s technology can increase flexibility and fast-time-to-market when compared to traditional ASICs and increase performance and lower power consumption when compared to FPGAs. By integrating hardware accelerator solutions with the eASIC platform, Intel can deliver much faster and more flexible systems for cloud customers.
“Having the ability to highly customize our solutions for a given workload will not only make the specific application run faster, but also help accelerate the growth of exciting new applications like visual search,” said Diane Bryant, senior vice president and general manager of Intel’s Data Center Group. “This announcement helps broaden our portfolio of customized products to provide our customers with the flexibility and performance they need.”
where are the customers rushing to implement FinFet ?
the foundry model is not broken?
It's dead in a traditional way - only very few customer will move to finfets
perhaps the foundry model is changing - more like an IDM....like Samsung
and always show me the capex - TSMC announced record capex and than they cut capex in Q1 - show me the money
It has something to do with the cost structure of semiconductor manufacturing ....
the majority is fix cost and most if not all is already absorbed by server and PC chips - I know that's hard to comprehend ....besides Intel has superior yields.
Assuming one has (depreciated) capacity one cranks out chips as long as the ASP exceeds the variable cost...and variable cost are low because of Intel's superior yields
Applied Materials said it will drop its $9.39 billion bid for Tokyo Electron after the U.S. Department of Justice told the companies their proposal would not be sufficient to replace the competition lost in the merger.
Intel did not like it and although AMAT has very good senior management I don't understand that they did not see this coming.
Maybe someone will be interested in KLAC
I suppose you saw the report from "Chipworks" - supposedly an update and "stay tuned" but nothing new over the last couple weeks and NO cross sections from TSMC.....
Do you agree Apple would need two designs?
one for Samsung process and one for TSMC process?
At least that opinion was shared by some "Appleinsiders" and one analyst mentioned it as well
I think Intel intends to order a minimum of 15 -
If this is the case I am afraid ASML is sold out -
what do you think is the leadtime of EUV stepper?
18 months ?