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Intel Corporation Message Board

semi_equip_junkie 165 posts  |  Last Activity: 1 hour 3 minutes ago Member since: Feb 16, 2012
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  • semi_equip_junkie semi_equip_junkie Jan 26, 2014 1:01 AM Flag

    I don't read that as exhuberant good news for Intel.
    It's dog eats dog world...
    It's good and bad for Intel - EUV won't be ready @10nm for Intel but Intel has a contingency plan - 10nm as far as I understand is already "locked in" - Intel will use quadruple patterning for critical layers - TSMC wlll be stressed to the max... and remember TSMC won't do the heavy lifting by themself - regardless what Nenni is telling the world the foundry model the way we know from the past is dead - the big fish like QCOM will have to provide funding - but this opens a new case of worms - there will be first class customer (the one who provide funding) and there will be second and third class


    If EUV can’t be brought online in the near future, the major semiconductor manufacturers will be talking about quad-patterning by 14-16nm – and that’s enough of a cost increase that it could seriously damage the foundry model altogether. As the number of patterns increases, the chance of a mistake in mask-switching is higher, and with the space between transistors shrinking, even a tiny mistake will cause unsustainable defects.

  • semi_equip_junkie by semi_equip_junkie Jan 25, 2014 12:24 PM Flag

    Handel also sees uncertainly in the use of FinFET devices due to higher wafer cost. “We see quite a few new designs. The problem again is the cost per wafer. For 28nm, we have about $2600 and for 20nm we have about $3200 and for 16/14 we have about $4000. You now have this increasing cost per wafer and can you get the higher gate density and can you also get higher parametric yields?” he asked.

    This guy is part of ARM eco system - I suppose the bashers must be going nuts - WW is right - it's about manufacturing

  • semi_equip_junkie semi_equip_junkie Jan 25, 2014 12:18 PM Flag

    Excellent read - I am sure Intel investors will be able to figure out where to find it - hint NOT on Semiwikki

    Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

  • jamulmike • 18 hours ago

    0 users liked this posts users disliked this posts 0
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    MSCC CC: Wants a piece of FPGA biz

    James J. Peterson - Chairman, Chief Executive Officer and Chairman of Executive Committee
    I want to add a little bit on the FPGAs. We have a very aggressive program in the SoC FPGAs. We're working very closely with those that help make the market possible, and that is what you call the distributor channel, where we've currently accelerated the number of certified engineers at both Arrow and Avnet, as well as adding onto to our depth of engineers for FPGAs. It might sound bold, but my plan in that market space is to help Altera and Xilinx not have to worry about being a duopoly. Less

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