SAN JOSE, CA--(Marketwired - Oct 1, 2013) - Cadence Design Systems, Inc. (
Cadence received an award for the "Analog/Mixed-Signal IP" category. The winners of the IP award are chosen based on customer feedback, TSMC9000 compliance, number of tapeouts, wafer volume and support. Cadence has a mature and broad offering of analog/mixed-signal IP including 28nm IP designs.
The award for "Joint Development of 16nm FinFET Design Infrastructure" is a validation of a long-standing relationship between Cadence and TSMC, working together on advanced node technology development and specifically FinFET enablement. The "Joint Delivery of 3D-IC Design Solution" award is in recognition of the joint collaboration on the new 3D-IC reference flow, and TSMC's first innovative, true 3D stacking 3D-IC testchip tapeout.
"The awards Cadence received were based on the quality results that were delivered for IP, 16nm FinFET and 3D-IC solutions," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing. "We look forward to continuing our partnership and delivering innovative design solutions to our mutual customers in the years to come."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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