Media Alert: Cadence to Unveil New IO-SSO Analysis Suite at EPEPS Conference

Marketwired

SAN JOSE, CA--(Marketwired - Oct 21, 2013) - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, will give the first public demonstrations of its new IO-SSO Analysis Suite at the EPEPS conference Oct. 27 to Oct. 30 in San Jose. EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems.

WHAT: The Cadence IO-SSO Analysis Suite is a single-vendor solution that provides accurate system-level simultaneous switching noise (SSN) analysis, addressing coupled signal, power and ground networks across chips, packages and printed circuit boards (PCB). It delivers an unparalleled combination of accuracy, speed and ease of use.

The IO-SSO (input/output simultaneous switching outputs) Analysis Suite complements Cadence® implementation tools and provides a complete solution for multi-fabric extraction, system-level connectivity and high-speed DDR interface simulation that includes the effects of SSN. Cadence is unique in its ability to deliver implementation, extraction and simulation across chip, package and PCB.

In addition to the new product, visitors to the Cadence table 5 can learn more about the latest advances coming from the integration between Allegro® and Sigrity™ technology for both signal and power integrity.

WHEN:
Sunday, Oct. 27, to Wednesday, Oct. 30, 2013

Cadence experts also will speak at several sessions:

Monday, Oct. 28:

3:40 p.m. to 4:40 p.m.--"Accelerate High-Speed I/O Design Closure with Distributed Chip I/O Interconnect Model." Speakers: Yun Dai, Patrick Ho, Tiejun Yu, Jiayuan Fang

4:40 p.m. to 6:10 p.m.--"Accurate Characterization of Lossy Interconnects from TDR Waveforms." Speakers: Ping Liu, Jingping Zhang, Jiayuan Fang

Wednesday, Oct. 30:

11 a.m. to noon--"Low-Frequency, Enhanced S-Parameter Handling Scheme for Time-Domain Simulation of High-Speed Interconnects." Speakers: Chong Luo, Jingping Zhang, Jiayuan Fang

WHERE:
DoubleTree by Hilton Hotel
2050 Gateway Place
San Jose, CA 95110

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products and services is available at www.cadence.com.

© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Allegro, Sigrity, and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Contact:
For more information, please contact:
Cadence Newsroom
408-944-7226
newsroom@cadence.com

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