SAN JOSE, CA--(Marketwired - Jul 16, 2013) - Cadence Design Systems, Inc. (
- New flows incorporate the industry's leading DFM prevention, analysis, and signoff capabilities
- Cadence technologies selected after extensive benchmark testing
- DFM solutions to boost productivity and enhance yield for customers
Cadence Design Systems, Inc. (
At 28nm and beyond, it is critical to accurately predict and automatically fix DFM "hotspots" to accelerate time-to-yield. UMC joins a growing list of leading foundries standardizing on Cadence DFM solutions to boost productivity and yield for customers. The DFM signoff technologies tightly integrate into the Encounter® digital and Cadence Virtuoso® custom/analog implementation and sign-off solutions. This solution delivers a "correct-by-design" capability for customers that models and analyzes the physical and parametric impact of lithography, Chemical-Mechanical Polishing (CMP), and layout dependent effects, and then optimizes the implementation to mitigate the physical and electrical variation on the designs, allowing users to reach their time-to-volume goals.
"To meet our time-to-market goals, DFM solutions at 28nm need to deliver low cost of ownership, accurate silicon predictability and high performance," said S.C. Chien, vice president of IP & Design Support division at UMC. "After rigorous evaluation, the Cadence DFM technology was selected for its exceptional characteristics in both physical and electrical DFM analysis. Now, we can offer our customers much greater predictability and faster turnaround time for their advanced node designs."
"At advanced nodes, prevention of potential DFM hotspots and yield limiters before tapeout is imperative to achieving first-silicon success and the highest silicon yields," said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. "Working in tight partnership with UMC, we continue to invest in technologies that strengthen our leadership in sign-off technologies, like providing DFM-aware implementation flows for current and future nodes."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Encounter, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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