SAN DIEGO--(BUSINESS WIRE)--
Chronos Tech, a privately owned leader in Intellectual Property solutions serving the semiconductor industry, announced today they launched Chronos Link, a groundbreaking technology for efficiently and effortlessly connecting Intellectual Properties (IPs) on complex System on Chip (SoC).
Modern technology requires large data throughput, forcing increased connectivity and large data transfers between various IP blocks. Nevertheless, metal layers in FinFET technologies are not scaling as fast as device layers. In fact, it is not uncommon to have 20% of the total SoC area used to connect the remaining 80%. “This is creating a major bottleneck for the underlying fabric,” says Stefano Giaconi, Chronos Tech’s Chief Technology Officer. “Routing congestion is rapidly becoming the limiting factor in deciding which features can be included as part of the overall SoC design.”
Chronos Link is specifically designed to enable robust on-chip and off-chip communication while significantly reducing interconnect overheads. As the number of integrated IPs increases, the interconnects between them grows at an exponential pace. Chronos Tech’s patented technology is founded on four synergistic elements:
- Delay-insensitive channels
- Clockless temporal compression
- Compatibility with industry standard SoC protocols
- AccuGauge-embedded performance measurement technology
The end result is effortless integration of IPs, substantial area reduction, and resilience to different Process, Voltage, and Temperature (PVT) conditions. According to Giacomo Rinaldi, VP of Engineering, “Chronos Tech’s unique mix of core elements enables SoC architects to reclaim up to 10% of die area while increasing yield, power efficiency, and data security.” He claims, “As the benefits increase with technology scaling, the potential savings are unprecedented.”
Chronos Link is currently gaining strong interest from leading semiconductor companies.
About Chronos Tech
San Diego-based Chronos Tech is a leader in IPs and architectural solutions that enable the development of next-generation complex SoCs. They leverage existing validated design flows with cutting-edge circuit innovations that can be optimized for routing, latency, and power. For more information, visit www.chronostech.com.