SAN JOSE, CA--(Marketwired - Nov 18, 2013) - Cadence Design Systems, Inc. (
Faraday successfully reduced the time for each prototyping run of this SoC design from two weeks to 3-5 days by leveraging the Encounter Digital Implementation (EDI) System, including GigaOpt multithreaded optimization and advanced analysis, Encounter Conformal® Equivalence Checker (EC) for hierarchical EC compare methodology, and integrated signoff tools for RC extraction and timing analysis.
Additional Cadence products used include Incisive® Enterprise Simulator, Verification Intellectual Property (VIP), Encounter Power System, Allegro® Package Designer and Allegro Sigrity™ signal and power integrity solutions.
"This SoC was the biggest project we've undertaken, and is the most complex one ever in Taiwan, so we compiled the best tool set we could to ensure success -- in performance, quality and in time to market," said Jason Hung, RD vice president of Faraday. "Cadence's wide array of digital implementation and verification products plus the level of support we received helped us achieve all our goals."
For more information about this project, click here. Faraday plans to discuss this project at Embedded Technology 2013 Conference and Exhibition in Yokohama, Japan, Nov. 20-22.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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