SAN JOSE, CA--(Marketwire - Feb 21, 2013) - Cadence Design Systems, Inc. (
Visitors to the Cadence® booth (#1102) can learn about verification at the IC, SoC and system levels and the company's latest advances in verification IP.
Additional Cadence participation:
- A lunch panel, at noon Feb. 27 in the Pine/Cedar Ballroom, on "Best Practices in Verification Planning," moderated by John Brennan of Cadence and featuring panelists from Xilinx, Maxim Integrated Products, Verilab, Paradigm Works, Oski Technology, and Cadence.
- An industry leaders panel, at 3:30 p.m. Feb. 27 in the Oak/Fir Ballroom, titled, "The Road to 1M Design Starts," featuring Ziv Binyamini, Cadence corporate vice president, Systems and Software Solutions.
- A Cadence-led session from 8:30 a.m. to noon Feb. 28, in the Donner Ballroom, titled, "Fast Track Your UVM Debug Productivity with Simulation and Acceleration."
Feb. 25-28, 2013
2050 Gateway Place
San Jose, Calif. 95110
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, automotive electronics, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.