ALAMEDA, CA--(Marketwired - Aug 13, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added Verific's SystemVerilog parser as front-end support to version 2.7.1 of its Stylus® compiler.
Tabula, advancing high-performance programmable logic solutions for network infrastructure systems, announced that its recently released version of the Stylus compiler can process code written with SystemVerilog syntax through the use of the SystemVerilog parser.
"Verific's SystemVerilog and VHDL parsers are among the best architected and implemented software packages in EDA," says Karen Pieper, Tabula's director of software, who has extensive experience parsing Verilog and VHDL. "Our upgrade from Verilog to SystemVerilog went extremely smoothly."
Rob Dekker, Verific's founder and chief technology officer, expressed his congratulations to Tabula on adding SystemVerilog support to the Stylus compiler and remarks, "Over the years, we have developed a close working relationship with Tabula that we value."
"Through our successful and longstanding partnership with Verific, we were able to offer SystemVerilog functionality and support to our customers quickly," adds Steffan Rochel, vice president of software development at Tabula. "Verific's R&D team operates as a seamless extension of our own team and through our combined level of expertise, we will continue to deliver breakthrough products to our customers."
Verific's software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Verific's Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org. Website: www.verific.com. Follow Verific on Facebook: http://www.facebook.com/pages/Verific-Design-Automation/100448363329771.
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