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Verific Design Automation's Board Member Honored With DATE Fellow Award

ALAMEDA, CA--(Marketwired - Mar 9, 2016) - Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.

He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.

Gardner was an active member of the DATE Executive Committee and Sponsor's Committee, representing the EDA Consortium, where he served as executive director from 2006 until 2015. He was the co-chair of DATE's Management Day Track, served on the DATE Audit committee, and continues to be a strong advocate of the event.

DATE, held this year in Dresden, Germany, from March 14 until March 18, combines an electronic systems design and test conference with an international exhibition. Its focus ranges from electronic design, automation and test, system-level hardware and software implementation to integrated circuit design.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: info@verific.com Website: www.verific.com

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